SYSTEM INTERFACE INFORMATION
Table 10 provides useful information about opti-
mizing system interface software.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Table 10
System Interface Information
OFFSET LENGTH DESCRIPTION
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
1
VCC logic supply minimum program/erase voltage
Bits 0–3 BCD 100mV
Bits 4–7 BCD volts
1
VCC logic supply maximum program/erase voltage
Bits 0–3 BCD 100mV
Bits 4–7 BCD volts
1
VPP [programming] supply minimum program/erase
voltage
Bits 0–3 BCD 100mV
Bits 4–7 Hex volts
1
VPP [programming] supply maximum program/erase
voltage
Bits 0–3 BCD 100mV
Bits 4–7 Hex volts
1
“n” such that typical single word program
timeout = 2n µs
1
“n” such that typical max. buffer write timeout = 2n µs
1
“n” such that typical block erase timeout = 2n ms
1
“n” such that typical full chip erase timeout = 2n ms
1
“n” such that maximum word program timeout = 2n
times typical
1
“n” such that maximum buffer write timeout = 2n
times typical
1
“n” such that maximum block erase timeout = 2n
times typical
1
“n” such that maximum chip erase timeout = 2n
times typical
ADDRESS HEX VALUE
CODE
1Bh
27
2.7V
1Ch
36
3.6V
1Dh
00
0.0V
1Eh
00
0.0V
1Fh
07
128µs
20h
07
128µs
21h
0A
1s
22h
00
N/A
23h
04
2ms
24h
04
2ms
25h
04
16s
26h
00
N/A
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
16
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©2002, Micron Technology, Inc.