MT28F128J3FS-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F128J3FS-12F' PDF : 52 Pages View PDF
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Table 13
Protection Register Information
OFFSET1
P = 31h
(P+E)h
(P+F)h
(P+10)h
(P+11)h
(P+12)h
DESCRIPTION
(OPTIONAL FLASH FEATURES AND COMMANDS)
Number of protection register fields in JEDEC ID space. “00h”
indicates that 256 protection bytes are available.
Protection Field 1: Protection Description
This field describes user-available, one-time programmable (OTP)
protection register bytes. Some are preprogrammed with device-
unique serial numbers; others are user-programmable. Bits 0–15
point to the protection register lock byte, the section’s first byte.
The following bytes are factory-preprogrammed and user-
programmable.
Bits 0–7 Lock/bytes JEDEC-plane physical low address
Bits 8–15 Lock/bytes JEDEC-plane physical high address
Bits 16–23 “n” such that 2n = factory preprogrammed bytes
Bits 24–31 “n” such that 2n = user-programmable bytes
ADDRESS
3Fh
HEX
01
VALUE
CODE
01
40h
00
00h
Table 14
Burst Read Information
OFFSET1
P = 31h
(P+13)h
(P+14)h
(P+15)h
DESCRIPTION
(OPTIONAL FLASH FEATURES AND COMMANDS)
ADDRESS
Page Mode Read Capability
44h
Bits 0–7 = “n” such that 2n Hex value represents the number of
read page bytes. See offset 28h for device word width to determine
page mode data output width. 00h indicates no read page buffer.
Number of synchronous mode read configuration fields
45h
that follow. 00h indicates no burst capability.
Reserved for future use.
46h
HEX
03
00
VALUE
CODE
8 byte
NOTE: 1. The variable “P” is a pointer which is defined at CFI offset 15h.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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