MT46V2M32 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT46V2M32' PDF : 65 Pages View PDF
CK#
CK
COMMAND
T0
WRITE
64Mb: x32
DDR SDRAM
T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n
WRITE
WRITE
WRITE
WRITE
NOP
ADDRESS
DQS
DQ
DM
Bank,
Col b
Bank,
Col x
tDQSS (NOM)
Bank,
Col n
Bank,
Col a
Bank,
Col g
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
b
b’
x
x’
n
n’
a
a’
g
g’
DON T CARE
TRANSITIONING DATA
NOTE: 1. DI b, etc. = data-in for column b, etc.
2. b’, etc. = the next data-in following DI b, etc., according to the programmed burst order.
3. Programmed burst length = 2, 4, or 8 in cases shown.
4. Each WRITE command may be to any bank.
Figure 18
Random WRITE Cycles
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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