MT46V2M32 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT46V2M32' PDF : 65 Pages View PDF
CK#
CK
COMMAND
T0
WRITE
ADDRESS
Bank a,
Col b
tDQSS (NOM)
DQS
tDQSS
DQ
DM
T1 T1n T2 T2n T3
NOP
NOP
NOP
tWTR
DI
b
T4
READ
Bank a,
Col n
tDQSS (MIN)
DQS
DQ
DM
tDQSS
DI
b
tDQSS (MAX)
DQS
tDQSS
DQ
DI
b
DM
64Mb: x32
DDR SDRAM
T5
T6 T6n
NOP
NOP
CL = 2
DI
n
CL = 2
DI
n
CL = 2
DI
n
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same bank. However, the READ and WRITE commands may be
to different devices, in which case tWTR is not required and the READ command could be applied earlier.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
Figure 19
WRITE to READ – Uninterrupting
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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