MT48H8M32LFBF-8LG View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8LG' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Operations
Figure 30: READ with Auto Precharge Interrupted by a WRITE
T0
T1
T2
CLK
COMMAND
READ - AP
BANK n
NOP
NOP
BANK n
Page
Active
READ with Burst of 4
Internal
States
BANK m
Page Active
ADDRESS
DQM1
BANK n,
COL a
DQ
CL = 3 (bank n)
T3
T4
T5
T6
NOP
WRITE - AP
NOP
NOP
BANK m
Interrupt Burst, Precharge
tRP - BANK n
WRITE with Burst of 4
BANK m,
COL d
DOUT
DIN
a
d
DIN
d+1
DIN
d+2
T7
NOP
Idle
t WR - BANK m
Write-Back
DIN
d+3
DON’T CARE
Note: DQM is HIGH at T2 to prevent DOUT a +1 from contending with DIN d at T4.
WRITE with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (see Figure 31 on page 39).
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (see Figure 32 on page 39).
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
38
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