MT48LC128M4A2P-75C View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-75C' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Operations
Figure 26: CLOCK SUSPEND During WRITE Burst
T0
T1
T2
T3
CLK
T4
T5
CKE
INTERNAL
CLOCK
COMMAND
NOP
WRITE
NOP
NOP
ADDRESS
BANK,
COL n
DIN
DIN
n
DIN
n+1
Transitioning Data
Note: BL = 4 or greater. DM is LOW.
Figure 27: CLOCK SUSPEND During READ Burst
T0
T1
T2
T3
T4
CLK
DIN
n+2
Don’t Care
T5
T6
CKE
INTERNAL
CLOCK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
Transitioning Data
Don’t Care
Note: CL = 2, BL = 4 or greater. DQM is LOW.
Burst READ/Single WRITE
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
34
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