MT48LC128M4A2P-75C View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-75C' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Operations
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing:
Accessing mode
register:
Precharging all:
Starts with registration of an AUTO REFRESH command and ends when
tRC is met. After tRC is met, the SDRAM will be in the all banks idle
state.
Starts with registration of a LOAD MODE REGISTER command and ends
when tMRD has been met. After tMRD is met, the SDRAM will be in the
all banks idle state.
Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
less of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
39
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