MT48LC128M4A2P-75C View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-75C' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Operations
Concurrent Auto Precharge
An access command to (READ or WRITE) another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a READ on bank n, CL later. The PRECHARGE to bank n will begin when the
READ to bank m is registered (see Figure 28).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (see Figure 29 on page 36).
Figure 28: READ with Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
READ - AP
BANK n
NOP
READ - AP
BANK m
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t RP - BANK n
READ with Burst of 4
NOP
NOP
Idle
tRP - BANK m
Precharge
ADDRESS
DQ
BANK n,
COL a
BANK m,
COL d
CL = 3 (BANK n)
Note: DQM is LOW.
DOUT
a
DOUT
a+1
DOUT
d
DOUT
d+1
CL = 3 (BANK m)
Transitioning Data
Don’t Care
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
35
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