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MT48LC16M4A2TG View Datasheet(PDF) - Micron Technology

Part Name
Description
MFG CO.
MT48LC16M4A2TG
Micron
Micron Technology Micron
'MT48LC16M4A2TG' PDF : 55 Pages View PDF
64Mb: x4, x8, x16
SDRAM
ALTERNATING BANK READ ACCESSES 1
T0
CLK
T1
tCK
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
DQM /
DQML, DQMH
A0-A9, A11
tAS tAH
ROW
T2
tCL
tCH
READ
tCMS tCMH
COLUMN m 2
T3
NOP
T4
T5
T6
T7
ACTIVE
NOP
READ
NOP
ROW
COLUMN b 2
T8
ACTIVE
ROW
A10
BA0, BA1
DQ
tAS tAH
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BANK 0
BANK 0
BANK 3
tAC
tAC
tOH
tAC
tOH
BANK 3
tAC
tOH
tAC
tOH
BANK 0
tAC
tOH
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
tLZ
CAS Latency - BANK 0
DOUT m
DOUT m + 1
DOUT m + 2
DOUT m + 3
tRP - BANK 0
DOUT b
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
SYMBOL*
tAC(3)
tAC(2)
tAH
tAS
tCH
tCL
tCK(3)
tCK(2)
tCKH
tCKS
MIN
1
1.5
2.5
2.5
6
1
1.5
MAX
5.5
-7E
MIN MAX
5.4
5.4
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
-75
MIN MAX
5.4
6
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
-8E
MIN MAX UNITS
6 ns
6 ns
1
ns
2
ns
3
ns
3
ns
8
ns
10
ns
1
ns
2
ns
-6
-7E
-75
-8E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
tCMH
1
0.8
0.8
1
ns
tCMS
1.5
1.5
1.5
2
ns
tLZ
1
1
1
1
ns
tOH
2
3
3
3
ns
tRAS
42 120,000 37 120,000 44 120,000 50 120,000 ns
tRC
60
60
66
70
ns
tRCD
18
15
20
20
ns
tRP
18
15
20
20
ns
tRRD
12
14
15
20
ns
*CAS latency indicated in parentheses.
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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