MT48LC4M32B2B5-7 View Datasheet(PDF) - Micron Technology
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MFG CO.
'MT48LC4M32B2B5-7' PDF : 79 Pages View PDF
128Mb: x32 SDRAM
Truth Tables
Table 17: Truth Table – CKE
Notes 1–4 apply to all parameters and conditions
Current State
Power-down
CKEn-1
L
CKEn
L
Commandn
X
Self refresh
X
Clock suspend
X
Power-down
L
H
COMMAND INHIBIT or NOP
Self refresh
COMMAND INHIBIT or NOP
Clock suspend
X
All banks idle
H
L
COMMAND INHIBIT or NOP
All banks idle
AUTO REFRESH
Reading or writing
VALID
H
H
See Table 16 (page 32).
Actionn
Maintain power-down
Maintain self refresh
Maintain clock suspend
Exit power-down
Exit self refresh
Exit clock suspend
Power-down entry
Self refresh entry
Clock suspend entry
Notes
5
6
7
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previ-
ous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of
COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
for clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges
occurring during the tXSR period. A minimum of two NOP commands must be provided
during the tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-
nize the next command at clock edge n + 1.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
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