MT48LC4M32B2B5-7 View Datasheet(PDF) - Micron Technology

Part Name

Description

MFG CO.

MT48LC4M32B2B5-7

1 Meg x 32 x 4 Banks SDR SDRAM

Micron Technology 

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128Mb: x32 SDRAM

Initialization

Note:

More than two AUTO REFRESH commands can be issued in the sequence. After steps 9

and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC

loops is achieved.

Figure 12: Initialize and Load Mode Register

CK ()()

((

CKE

))

((

))

((

COMMAND

))

((

))

T0

tCKS tCKH

tCMS tCMH

NOP2

T1

tCK

((

))

((

))

((

))

((

))

((

))

PRECHARGE ( (

))

Tn + 1

tCH

AUTO

REFRESH

DQM/DQML,

((

))

((

))

DQMU

((

))

((

))

A[9:0],

((

))

((

))

A[12:11]

((

))

((

))

((

A10

))

((

))

ALL BANKS

((

))

((

SINGLE BANK ) )

BA[1:0]

DQ

((

))

((

))

()()

T = 100µs

MIN

High-Z

((

ALL

))

BANKS ( (

))

()()

tRP

To + 1

((

))

tCL

((

))

()()

((

()()NOP2

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

AUTO

REFRESH

tRFC

Tp + 1

Tp + 2

((

))

((

))

()()

((

()()NOP2

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

LOAD MODE

REGISTER

tAS tAH5

CODE

tAS tAH

CODE

NOP2

tRFC

tMRD

Tp + 3

ACTIVE

ROW

ROW

Power-up:

VDD and

CLK stable

Precharge

all banks

AUTO REFRESH

AUTO REFRESH

Program Mode Register1,3,4

DON’T CARE

UNDEFINED

Notes:

1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.

2. If CS is HIGH at clock HIGH time, all commands applied are NOP.

3. JEDEC and PC100 specify three clocks.

4. Outputs are guaranteed High-Z after command is issued.

5. A12 should be a LOW at tP + 1.

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. U 04/13 EN

36

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2001 Micron Technology, Inc. All rights reserved.

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