MT48LC4M32B2B5-7 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2B5-7' PDF : 79 Pages View PDF
Burst Length
Burst Type
128Mb: x32 SDRAM
Mode Register
Read and write accesses to the device are burst oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2,
4, 8, or continuous locations are available for both the sequential and the interleaved
burst types, and a continuous page burst is available for the sequential type. The con-
tinuous page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with fu-
ture versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst wraps within the block when a boundary is reached. The block
is uniquely selected by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8.
The remaining (least significant) address bit(s) is (are) used to select the starting loca-
tion within the block. Continuous page bursts wrap within the page when the boundary
is reached.
Accesses within a given burst can be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst
type, and the starting column address.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
39
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© 2001 Micron Technology, Inc. All rights reserved.
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