MT48LC4M32B2P-7 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2P-7' PDF : 79 Pages View PDF
128Mb: x32 SDRAM
PRECHARGE Operation
Figure 43: WRITE Without Auto Precharge
T0
T1
T2
T3
CLK
tCK
tCKS tCKH
tCL
tCH
CKE
tCMS tCMH
Command
ACTIVE
NOP
WRITE
NOP
DQM
tCMS tCMH
Address
A10
BA0, BA1
tAS tAH
Row
tAS tAH
Row
tAS tAH
Bank
Column m
Disable auto precharge
Bank
DQ
tRCD
tRAS
tRC
tDS tDH
DIN
tDS tDH
DIN
T4
NOP
tDS tDH
DIN
T5
NOP
tDS tDH
DIN
T6
NOP
tWR
T7
PRECHARGE
All banks
Single bank
Bank
T8
NOP
tRP
T9
ACTIVE
Row
Row
Bank
Don’t Care
Note: 1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
69
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© 2001 Micron Technology, Inc. All rights reserved.
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