PRELIMINARY
256Mb: x32
SDRAM
POWER-DOWN MODE1
T0
CLK
T1
tCK
T2
tCL
((
))
tCH
tCKS
((
))
CKE
((
tCKS tCKH
))
tCMS tCMH
((
COMMAND PRECHARGE
NOP
NOP
))
((
))
((
DQM 0-3
))
((
))
((
A0-A9, A11
))
((
))
ALL BANKS
((
A10
))
((
SINGLE BANK
))
tAS tAH
((
))
BA0, BA1
BANK(S)
((
))
High-Z
DQ
Precharge all
active banks
Two clock cycles
All banks idle, enter
power-down mode
((
))
Input buffers gated off while in
power-down mode
Exit power-down mode
Tn + 1
tCKS
Tn + 2
NOP
ACTIVE
ROW
ROW
BANK
All banks idle
DON’T CARE
UNDEFINED
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
38
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©2003 Micron Technology, Inc.