PRELIMINARY
256Mb: x32
SDRAM
CLOCK SUSPEND MODE1
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCKS tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
T4
T5
T6
T7
T8
NOP
NOP
NOP
WRITE
DQM0-3
A0-A9, A11
tAS tAH
COLUMN m2
tCMS tCMH
COLUMN e2
tAS tAH
A10
BA0, BA1
tAS tAH
BANK
BANK
tAC
tAC
tOH
tHZ
tDS tDH
DQ
tLZ
DOUT m
DOUT m + 1
DOUT e
T9
NOP
DOUT e + 1
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. A9 and A11 = “Don’t Care.”
DON’T CARE
UNDEFINED
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
39
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©2003 Micron Technology, Inc.