P2V28S20ATP-7 View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'P2V28S20ATP-7' PDF : 51 Pages View PDF
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
AC TIMING REQUIREMENTS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V
Input Timing Measurement Level:1.4V
Symbol
Parameter
tCLK CLK cycle time
CL=2
CL=3
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
CLK High pulse width
CLK Low pulse width
Transition time of CLK
Input Setup time (all inputs)
Input Hold time (all inputs)
Row Cycle time
Refresh Cycle Time
Row to Column Delay
Row Active time
tRP
tWR
tRRD
tRSC
Row Precharge time
Write Recovery time
Act to Act Delay time
Mode Register Set Cycle time
tREF Refresh Interval time
-7
Min. Max.
-
7
2.5
2.5
1
10
1.5
0.8
63
70
20
45
100K
20
14
14
14
64
Limits
-75
Min. Max.
10
7.5
2.5
2.5
1
10
1.3
0.8
67.5
75
20
45
100K
20
15
15
15
64
-8
Unit
Min. Max.
10
ns
8
ns
3
ns
3
ns
1
10 ns
2
ns
0.8
ns
07
ns
80
ns
20
ns
48
100K ns
20
ns
20
ns
20
ns
20
ns
64 ms
CLK
DQ
1.4V
1.4V
Any AC timing is referenced
to the input signal passing
through 1.4V.
JULY.2000
Page-33
Rev.2.2
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