Networking Silicon — 82545GM
Table 6.b
Complete Subsystem (Reference SERDES Design)
Including LED, Regulator Circuits (no optics)
D3cold Wake Disabled
(Auxiliary Power)
D0 SERDES Active
(Primary Power)
3.3 V
2.5 V
1.5 V
Subsystem
3.3 V
Current
Typ Icc
(mA)
45
-0
5
Max Icc
(mA)
50
-0
5
55 mA
Typ Icc
(mA)
70
60
115
Max Icc
(mA)
80
70
130
280 mA
NOTE: In fiber/optical application or SERDES driven backplane application, power is substantially less than
when operating with a PHY/magnetics. For calculating thermal operations and in providing external
power-supply circuits for such applications, SERDES mode power is provided separately. Power is
specified into a load of 50 pF at default SERDES amplitude setting. Power consumed by optics module
(if present) is not included.
NOTE: Power specifications for uninitialized/disabled state are detailed under the copper MAC/PHY
specifications.
Table 7. I/O Characteristics
Symbol
VIL
VIH
VOL
VOH
VSH
IOLa
IOHa
IIN
IOZ
Parameter
Voltage input LOW
Voltage input HIGH
Voltage output LOW
Voltage output HIGH
Schmitt Trigger Hysteresis
Output current LOW
3mA drivers (TTL3)
6mA drivers (TTL6)
12mA drivers (TTL12)
Output current HIGH
3mA drivers (TTL3)
6mA drivers (TTL6)
12mA drivers (TTL12)
Input Current
TTL inputs
Inputs with pull-down resistors
TTL inputs with pull-up resistors
3-state output leakage current
Condition
VOL
VOL
VOL
VOH
VOH
VOH
VIN = VDD or VSS
VIN = VDD
VIN = VSS
VOH = VDD or VSS
Min
-0.5
2.0
2.4
0.1
3
6
12
-3
-6
-12
-10
150
-150
-10
Typ
Max Unit
0.8
V
VDD
+0.3
V
0.4
V
V
V
mA
mA
mA
mA
mA
mA
10
A
1
480 A
-480 A
1
10
A
Datasheet
27