Networking Silicon — 82545GM
Figure 4. PCI/PCI-X Clock Timing
3.3 V Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
Th
0.6 Vcc
Tcyc
0.2 Vcc
Tl
0.4 Vcc p-to-p
(minimum)
5.6.1.2
PCI/PCI-X Bus Interface Timing
Table 16. PCI/PCI-X Bus Interface Timing Parameters
Symbol
Parameter
TVAL
TVAL
(ptp)
TON
TOFF
TSU
TSU
(ptp)
TH
TRRSU
TRRH
CLK to signal valid delay:
bussed signals
CLK to signal valid delay:
point-to-point signals
Float to active delay
Active to float delay
Input setup time to CLK:
bussed signals
Input setup time to CLK:
point-to-point signals
Input hold time from CLK
REQ64# to RST# setup
time
RST# to REQ64# hold
time
PCI-X 133
MHz
Min Max
0.7 3.8
0.7 3.8
0
7
1.2
1.2
0.5
10*
TCYC
0
PCI-X 66 MHz PCI 66MHz
Min Max Min Max
0.7 3.8
2
6
0.7 3.8
2
6
0
2
7
14
1.7
3
1.7
0.5
10*
TCYC
0
5
0
10*
TCYC
0
PCI 33 MHz
Min Max
2
11
2
12
2
28
7
10,
12
0
10*
TCYC
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
Datasheet
31