PC8260 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'PC8260' PDF : 53 Pages View PDF
Table 4. External Signals (Continued)
Pin
Signal Name
DBG
60x Data Bus Grant
DBB
IRQ3
60x Data Bus Busy
D[0:63]
DP[0]
RSRV
EXT BR2
IRQ1
DP[1]
EXT BG2
Interrupt Request 3
60x Data Bus
60x Data Parity 0
Reservation
External Bus Request 2
Interrupt Request 1
60x Data Parity 1
IRQ2
DP[2]
TLBISYNC
EXT DBG2
External Bus Grant 2
Interrupt Request 2
60x Data Parity 2
TLB Sync:
External Data Bus Grant 2
Type
I/O
I/O
I
I/O
I/O
O
I
I
I/O
O
I
I/O
I
O
Description
This is an output when an internal arbiter is used and an input when an
external arbiter is used. As an output, the PowerQUICC II asserts this
pin to grant 60x data bus ownership to an external bus master. As an
input, the external arbiter should assert this pin to grant 60x data bus
ownership to the PowerQUICC II.
As an output the PowerQUICC II asserts this pin for the duration of the
data bus tenure. Following a TA, which terminates the data bus tenure,
the PowerQUICC II negates DBB for a fraction of a bus cycle and then
stops driving this pin. As an input, the PowerQUICC II will not assume
60x data bus ownership, as long as it senses this pin is asserted by an
external 60x bus master.
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
In write transactions, the 60x bus master drives the valid data on this
bus. In read transactions, the 60x slave drives the valid data on this bus.
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 0 pin should provide odd
parity (odd number of 1’s) on the group of signals that include data parity
0 and D[0:7].
The value driven on this output pin represents the state of the coherency
bit in the reservation address register that is used by the Iwarx and
stwcx. instructions.
An external master should assert this pin to request 60xbus ownership
from the internal arbiter.
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 1 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 1 and D[8:15].
The PowerQUICC II asserts this pin to grant 60x bus ownership to an
external bus master.
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 2 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 2 and S[16:23].
This input pin can be used to synchronize 60x core instruction execution
to hardware indications. Asserting this pin will force the core to stop
instruction execution following a tlbsinc instruction execution. The core
resumes instruction execution once this pin is negated.
The PowerQUICC II asserts this pin to grant 60x data bus ownership to
an external bus master.
22 PC8260 PowerQUICC II
2131B–HIREL–02/03
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