PC8260 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'PC8260' PDF : 53 Pages View PDF
Table 4. External Signals (Continued)
Pin
Signal Name
L_A22
PCI_SERR
Local Bus Address 22
PCI System Error
L_A23
PCI_REQ0
Local Bus Address 23
PCI Arbiter Request 0
L_A24
PCI_REQ1
L_A25
PCI_GNT0
Local Bus Address 24
PCI Arbiter Request 1
Local Bus Address 25
PCI Arbiter Grant 0
L_A26
PCI_GNT1
L_A27
CLKOUT
Local Bus Address 26
PCI Arbiter Grant 1
Local Bus Address 27
Clock Output pin
L_A28
PCI_RST
CORE_SRESET
Local Bus Address 28
PCI Reset
Core System Reset
PC8260 PowerQUICC II
Type
O
I/O
O
I/O
O
I
O
I/O
O
O
O
O
O
I/O
I
Description
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
Assertion of this pin indicates that a PCI system error was detected
during a PCI transfer.
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
When PowerQUICC II’s internal PCI arbiter is used, this is an input pin.
In this mode assertion of this pin indicates that an external PCI agent is
requesting the PCI bus. When an external PCI arbiter is used, this is an
output pin. In this mode assertion of this pin indicates that PowerQUICC
II’s PCI interface is requesting the PCI bus.
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
When PowerQUICC II’s internal PCI arbiter is used, assertion of this pin
indicates that an external PCI agent is requesting the PCI bus.
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
When PowerQUICC II’s internal PCI arbiter is used, this is an output pin.
In this mode, assertion of this pin indicates that an external PCI agent
that requested the PCI bus with the REQ0 pin is granted the bus. When
an external PCI arbiter is used, this is an input pin. In this mode,
assertion of this pin indicates that PowerQUICC II’s PCI interface is
granted the PCI bus.
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
When PowerQUICC II’s internal PCI arbiter is used, assertion of this pin
indicates that the external PCI agent that requested the PCI bus with the
REQ1 pin is granted the bus.
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
In a PCI system where PC8260’s PCI interface is configured to operate
from an external PCI clock, the 60x bus clock is driven on CLKOUT. In a
PCI system where the PC8260’s PCI interface is configured to generate
the PCI clock, the PCI clock is driven on CLKOUT. The PCI clock
frequency range is 25-66MHz.
In the local address bus bit 14 is most significant and bit 31 is least
significant.
When the PC8260 is the host in the PCI system, PCI_RST is an output.
When the PC8260is not the host of the PCI system, PCI_RST is an
input.
This an input to the core. When this input pin is asserted the core
branches to its reset vector.
29
2131B–HIREL–02/03
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