PC8260 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'PC8260' PDF : 53 Pages View PDF
Table 4. External Signals (Continued)
Pin
Signal Name
L_A14
PCI_PAR
Local Bus Address 14
PCI Parity
L_A15
PCI_FRAME
SMI
Local Bus Address 15
PCI Frame i
L-A16
PCI_TRDY
System Management
Interrupt
Local Bus Address 16
PCI Target Ready
L_A17
PCI_IRDY
CKSTP_OUT
Local Bus Address 17
PCI Initiator Ready
L_A18
PCI_STOP
Checkstop Output
Local Bus Address 18
PCI Stop
L_A19
PCI_DEVESEL
Local Bus Address 19
PCI Device Select
L_A20
PCI_IDSEL
L_A21
PCI_PERR
Local Bus Address 20
PCI ID select
Local Bus Address 21
PCI Parity Error
Type
O
I/O
O
I/O
I
Description
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
Assertion of this pin indicates that odd parity is driven across
PCI_AD[0:31] and PCI_C/BE[0-3] during address and data phases.
Negation of this pin indicates that even parity is driven across the
PCI_AD[0-31] and PCI_C/BE[0-3] signals during address and data
phases.
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
This pin is driven by the PowerQUICC II when its interface is the initiator
of a PCI transfer. This pin is asserted to indicate that a PCI transfer is on
going.
System management interrupt input to the core.
O In the local address bus, bit 14 is most significant and bit 31 is least
significant.
I/O This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that the PCI target
is ready to send or accept a data beat.
O In the local address bus, bit 14 is most significant and bit 31 is least
significant.
I/O This pin is driven by the PowerQUICC II when its PCI interface is the
initiator of a PC] transfer. Assertion of this pin indicates that the PCI
initiator is ready to send or accept a data beat.
O
Assertion of CKSTP_OUT indicates the core is in checkstop mode.
O In the local address bus, bit 14 is most significant and bit 31 is least
significant.
I/O This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that the PCI target
is requesting to stop the PCI transfer.
O In the local address bus, bit 14 is most significant and bit 31 is least
significant.
I/O This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that a PCI target
has recognized a new PCI transfer with an address that belongs to the
PCI target.
O In the local address bus, bit 14 is most significant and bit 31 is least
significant.
I
Used to select PowerQUICC II’s PCI interface during a PCI configuration
cycle.
O In the local address bus, bit 14 is most significant and bit 31 is least
significant.
I/O Assertion of this pin indicates that a parity error was detected during a
PCI transfer.
28 PC8260 PowerQUICC II
2131B–HIREL–02/03
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