PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
9.7 Set bias system
The bias voltage levels are set in the ratio of R − R − n × R − R − R (see Figure 11).
R
R
n×R
R
R
Fig 11. Voltage divider chain
V1 = VLCD
V2
V3
V4
V5
V6 = VSS
013aaa183
Different multiplex rates require different bias settings. Bias settings are programmed by
BS[2:0], which sets the binary number n. The optimum value for n is given by:
n = muxrate – 3
Supported values of n are given in Table 8. Table 9 shows the intermediate bias voltages.
Table 8.
BS[2:0]
000
001
010
011
100
101
110
111
Programming the required bias system
n
Bias system
7
1⁄11
6
1⁄10
5
1⁄9
4
1⁄8
3
1⁄7
2
1⁄6
1
1⁄5
0
1⁄4
Comment
-
-
-
-
recommended for 1:34
recommended for 1:26
recommended for 1:17
recommended for icon mode
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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