PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
10. I2C-bus interface
10.1 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
10.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 14).
SDA
SCL
Fig 14. Bit transfer
data line
stable;
data valid
change
of data
allowed
mbc 621
10.1.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in Figure 15.
SDA
SDA
SCL
S
START condition
Fig 15. Definition of START and STOP conditions
P
STOP condition
SCL
mbc 622
10.1.3 System configuration
The system configuration is shown in Figure 16.
• Transmitter: the device that sends the data to the bus
• Receiver: the device that receives the data from the bus
• Master: the device that initiates a transfer, generates clock signals and terminates a
transfer
• Slave: the device addressed by a master
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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