PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
• Multi-master: more than one master can attempt to control the bus at the same time
without corrupting the message
• Arbitration: procedure to ensure that, if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock signals of two or more devices.
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
SLAVE
RECEIVER
Fig 16. System configuration
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
mga807
10.1.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 17.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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