PCF8533 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8533' PDF : 45 Pages View PDF
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8533 are timed by a frequency fclk,
which either is derived from the built-in oscillator frequency fosc or equals an external clock
frequency fclk(ext).
fclk
=
-f-o---s--c
64
The clock frequency fclk determines the LCD frame frequency ffr (see Table 6) and is
calculated as follows:
ffr
=
-f-c---l--k
24
Table 6. LCD frame frequency
Nominal clock frequency (Hz)
LCD frame frequency (Hz)
1 536
64
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output
from pin CLK provides the clock signal for cascaded PCF8533s in the system.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCF8533 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the synchronization signal (SYNC) maintains the correct timing relationship
between the PCF8533s in the system. The timing also generates the LCD frame signal
(ffr) whose frequency is derived as an integer division of the clock frequency fclk (see
Table 6), applied to pin CLK from either the internal or an external clock.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and each column of the display RAM.
7.8 Segment outputs
The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display register. If less than
80 segment outputs are required, the unused segment outputs must be left open-circuit.
PCF8533_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 5 March 2010
© NXP B.V. 2010. All rights reserved.
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