PCF8533 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8533' PDF : 45 Pages View PDF
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
data output
by transmitter
data output
by receiver
SCL from
master
S
1
2
START
condition
Fig 14. Acknowledgement on the I2C-bus
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
mbc602
8.1.4 I2C-bus controller
The PCF8533 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8533 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, the transferred command data and the hardware subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
8.1.5 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.1.6 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8533.
The least significant bit of the slave address is bit R/W. The PCF8533 is a write-only
device. It will not respond to a read access, so this bit should always be logic 0. The
second bit of the slave address is defined by the level tied at input SA0. Two displays
controlled by PCF8533 can be recognized on the same I2C-bus which allows:
• Up to 16 PCF8533s on the same I2C-bus for very large LCD applications
• The use of two types of LCD multiplex drive mode on the same I2C-bus
The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the available PCF8533
slave addresses. All PCF8533s with the same SA0 level acknowledge in parallel to the
slave address. All PCF8533s with the alternative SA0 level ignore the whole I2C-bus
transfer.
PCF8533_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 5 March 2010
© NXP B.V. 2010. All rights reserved.
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