PCF8533 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8533' PDF : 45 Pages View PDF
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
7.9 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode: The same signal is carried by all four backplane outputs; and
they can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 80 × 4 bit RAM which stores LCD data. A logic 1 in the RAM
bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0
indicates the off state. There is a one-to-one correspondence between the RAM
addresses and the segment outputs and between the individual bits of a RAM word and
the backplane outputs. The display RAM bit map Figure 9 shows rows 0 to 3 which
correspond with the backplane outputs BP0 to BP3, and columns 0 to 79 which
correspond with the segment outputs S0 to S79. In multiplexed LCD applications the
segment data of the first, second, third and fourth row of the display RAM are
time-multiplexed with BP0, BP1, BP2, and BP3 respectively.
display RAM addresses (columns) / segment outputs (S)
01234
75 76 77 78 79
0
display RAM bits
(rows) /
1
backplane outputs
(BP)
2
3
mgl750
Fig 9. Display RAM bit map showing direct relationship between RAM address and
segment outputs and also between RAM word bits and backplane outputs
When display data is transmitted to the PCF8533, the received display bytes are stored in
the display RAM in accordance with the selected LCD drive mode. The data is stored as it
arrives and does not wait for the acknowledge cycle as with the commands. Depending on
the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples.
To illustrate the filling order, an example of a 8-segment numeric display showing all drive
modes is given in Figure 10; the RAM filling organization depicted applies equally to other
LCD types.
PCF8533_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 5 March 2010
© NXP B.V. 2010. All rights reserved.
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