PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
PCF8536AT/1
NXP Semiconductors.
'PCF8536AT/1' PDF : 74 Pages View PDF
NXP Semiconductors
PCF8536
Universal LCD low multiplex driver with 6 channel PWM generator
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 35.
data output
by transmitter
data output
by receiver
SCL from
master
S
1
2
START
condition
Fig 35. Acknowledgement on the I2C-bus
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
mbc602
9.2.5 I2C-bus controller
The PCF8536 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. Device selection depends on the I2C-bus
slave address.
9.2.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
PCF8536
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 6 October 2011
© NXP B.V. 2011. All rights reserved.
48 of 74
Share Link: 