Philips Semiconductors
(67 + 1) × 102 pixels matrix LCD driver
Product speciï¬cation
PCF8813
10 I2C-BUS INTERFACE (Hs-MODE)
10.1 Characteristics of the I2C-bus (Hs-mode)
The I2C-bus Hs-mode is for bidirectional, two-line
communication between different ICs or modules with
speeds up to 3.4 MHz. The only difference between
Hs-mode slave devices and Fast-mode slave devices is
the speed at which they operate, therefore the buffers on
the SLCH and SDAH outputs(1) have an open-drain. This
is the same for I2C-bus master devices which have an
open-drain SDAH output and a combination of open-drain
pull-down and current source pull-up circuits on the SCLH
output. Only the current source of one master is enabled
at any one time, and only during Hs-mode. Both lines must
be connected to a positive supply via a pull-up resistor.
Data transfer may be initiated only when the bus is not
busy.
10.1.1 SYSTEM CONFIGURATION
• Transmitter: the device that sends the data to the bus
• Receiver: the device that receives the data from the bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
• Slave: the device addressed by a master
• Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
• Synchronisation: procedure to synchronize the clock
signals of two or more devices.
(1) In Hs-mode, SCL and SDA lines operating at the higher
frequency are referred to as SCLH and SDAH.
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
Fig.25 System configuration.
MGA807
10.1.2 BIT TRANSFER
One data bit is transferred during each clock pulse (see
Fig.26). The data on the SDAH line must remain stable
during the HIGH period of the clock pulse as changes in
the data line at this time will be interpreted as control
signals.
handbook, full pagewidth
SDA
SCL
2004 Mar 05
data line
stable;
data valid
change
of data
allowed
Fig.26 Bit transfer.
23
MBC621