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PCF8813 View Datasheet(PDF) - Philips Electronics

Part Name
Description
MFG CO.
PCF8813
Philips
Philips Electronics Philips
'PCF8813' PDF : 72 Pages View PDF
Philips Semiconductors
(67 + 1) × 102 pixels matrix LCD driver
Product speciï¬cation
PCF8813
10.2 I2C-bus Hs-mode protocol
The PCF8813 is a slave receiver/transmitter. If data is to
be read from the device the SDAH pad must be connected,
otherwise SDAHOUT may be unused.
Hs-mode can only commence after the following
conditions:
• START condition (S)
• 8-bit master code (00001XXX)
• Not-acknowledge bit (A).
The master code has two functions, as shown in Figs 29
and 30, it allows arbitration and synchronization between
competing masters at Fast-mode speeds, resulting in one
winner. Also the master code indicates the beginning of an
Hs-mode transfer.
As no device is allowed to acknowledge the master code,
the master code is followed by a not-acknowledge (A).
After this A-bit, and the SCLH line has been pulled up to a
HIGH level, the active master switches to Hs-mode and
enables at tH the current-source pull-up circuit for the
SCLH signal (see Fig.30).
The active master will then send a repeated START
condition (Sr) followed by a 7-bit slave address with a
R/W-bit, and receives an acknowledge bit (A) from the
selected slave. After each acknowledge bit (A) or
not-acknowledge bit (A) the active master disables its
current-source pull-up circuit. The active master
re-enables its current source again when all devices have
released and the SCLH signal reaches a HIGH level. The
rising of the SCLH is done by a resistor pull-up and so
slower, the last part of the SCLH rise time is speeded up
because the current-source is enabled. Data transfer only
switches back to Fast-mode after a STOP condition (P).
A write sequence after the Hs-mode is selected is given in
Fig.29. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by
the slave address. All slaves with the corresponding
address acknowledge in parallel, all the others will ignore
the I2C-bus transfer.
After acknowledgement of a write (W) cycle, one or more
command words follow which define the status of the
addressed slaves. A command word consists of a control
byte, which defines CO and D/C, plus a data byte (see
Fig.31 and Table 4).
The last control byte is tagged with a cleared most
significant bit, the continuation bit Co. The control and data
bytes are also acknowledged by all addressed slaves on
the bus.
Table 4 CO and D/C deï¬nition
BIT 0/1 R/W
ACTION
CO 0 N/A last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may
only be terminated by a STOP or RE-START condition
1
another control byte will follow the data byte unless a STOP or RE-START condition is received
D/C 0
0 data byte will be decoded and used to set-up the device
1 data byte will return the status byte
1
0 data byte will be stored in the display RAM
1 RAM read back is not supported
After the last control byte, depending on the D/C bit setting,
a series of display data bytes or command data bytes may
follow. If the D/C-bit was set to logic 1, these display bytes
are stored in the display RAM at the address specified by
the data pointer. The data pointer is updated automatically
and the data is directed to the intended PCF8813. If the
D/C-bit of the last control byte was set to logic 0, these
command bytes will be decoded and the setting of the
device will be changed according to the received
commands. The acknowledgement after each byte is
made only by the addressed PCF8813. At the end of the
transmission the I2C-bus master issues a STOP
condition (P) and switches back to Fast-mode, however, to
reduce the overhead of the master code, its possible that
a master links a number of Hs-mode transfers, separated
by repeated START conditions (Sr).
A read sequence (see Fig.32) follows after the Hs-mode is
selected. The PCF8813 will immediately start to output the
requested data until a NOT acknowledge is transmitted by
the master. Before the read access, the user has to set the
D/C-bit to the appropriate value by a preceding write
access. The write access should be terminated by a
RE-START condition so that the HS-mode is not disabled.
2004 Mar 05
25
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