PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
Table 7–6 shows assertion of S_PERR# that is set under the following conditions:
• PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the secondary bus.
• The parity error response bit must be set in the bridge control register of secondary interface.
• PI7C7100 detects a data parity error on the secondary bus or detects P_PERR# asserted during the completion phase
of an upstream delayed write transaction on the target (primary) bus.
S_PERR#
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
02
0
Transaction
Type
Read
Read
Read
Read
Posted write
Posted write
Posted write
Posted write
Delayed write
Delayed write
Delayed write
Delayed write
Table 7–6. Assertion of S_PERR#
Direction
Bus where error
was detected
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary/Secondary
parity error response bits
x/x1
x/1
x/x
x/x
x/x
x/x
x/x
x/1
x/x
x/x
1/1
x/1
1x =don’t care
2The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
43
09/18/00 Rev 1.1
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