PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
10. Clocks
This chapter provides information about the clocks.
10.1 Primary Clock Inputs
PI7C7100 implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock
input, P_CLK, and the secondary interface is synchronized to the secondary clock. The secondary clock is derived internally
from the primary clock, P_CLK, through an internal PLL.
PI7C7100 operates at a maximum frequency of 33 MHz.
10.2 Secondary Clock Outputs
PI7C7100 has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as clock inputs for up to sixteen external
secondary bus devices. The S_CLKOUT[15:0] outputs are derived from P_CLK. The secondary clock edges are delayed
from P_CLK edges by a minimum of 0ns.
This is the rule for using secondary clocks:
• Each secondary clock output is limited to no more than one load.
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09/18/00 Rev 1.1
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