PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
Table 7–7 shows assertion of P_SERR#. This signal is set under the following conditions:
• PI7C7100 has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted
on a downstream posted write transaction.
• PI7C7100 did not detect the parity error as a target of the posted write transaction.
• The parity error response bit on the command register and the parity error response bit on the bridge control
register must both be set.
• The SERR# enable bit must be set in the command register.
Table 7–7. Assertion of P_SERR# for Data Parity Errors
P_SERR#
Transaction
Type
Direction
Bus where error was
detected
Primary/Secondary
parity error response bits
1 (de-asserted) Read
Downstream
Primary
x/x1
1
Read
Downstream
Secondary
x/x
1
Read
Upstream
Primary
x/x
1
Read
Upstream
Secondary
x/x
1
Posted write
Downstream
Primary
x/x
02 (asserted) Posted write
Downstream
Secondary
1/1
03
Posted write
Upstream
Primary
1/1
1
Posted write
Upstream
Secondary
x/x
1
Delayed write
Downstream
Primary
x/x
1
Delayed write
Downstream
Secondary
x/x
1
Delayed write
Upstream
Primary
x/x
1
Delayed write
Upstream
Secondary
x/x
1x =don’t care
2The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
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09/18/00 Rev 1.1
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