PIC14000T-04/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC14000T-04/SS' PDF : 153 Pages View PDF
PIC14000
TABLE 7-1: I2C BUS TERMINOLOGY
Term
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization
Description
The device that sends the data to the bus.
The device that receives the data from the bus.
The device which initiates the transfer, generates the clock, and terminates the transfer.
The device addressed by a master.
More than one master device in a system. These masters can attempt to control the bus
at the same time without corrupting the message.
Procedure that ensures that only one of the master devices will control the bus. This
ensures that the transfer data does not get corrupted.
Procedure where the clock signals of two or more devices are synchronized.
FIGURE 7-4: I2C 7-BIT ADDRESS FORMAT
MSb
LSb
S
R/W ACK
S
R/W
ACK
slave address
Start Condition
Read/Write pulse
Acknowledge
Sent by
Slave
FIGURE 7-5: I2C 10-BIT ADDRESS
FORMAT
S 1 11 1 0 A9 A8 RW ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
S - Start Condition
R/W - Read/Write Pulse
ACK - Acknowledge
sent by slave
= 0 for write
7.2 Addressing I2C Devices
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 7-4). The
address is the most significant seven bits of the byte.
For example when loading the I2CADD register, the
least significant bit is a “don’t care”. The more complex
is the 10-bit address with a R/W bit (Figure 7-5). For
10-bit address format, two bytes must be transmitted
with the first five bits specifying this to be a 10-bit
address.
DS40122B-page 44
Preliminary
© 1996 Microchip Technology Inc.
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