PIC14000T-04/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC14000T-04/SS' PDF : 153 Pages View PDF
PIC14000
7.5.1.1 ADDRESSING
Once the I2C module has been enabled, the I2C waits
for a START to occur. Following the START, the 8-bits
are shifted into the I2CSR. All incoming bits are
sampled with the rising edge of the clock (SCL) line.
The I2CSR<7:1> is compared to the I2CADD register.
The address is compared on the falling edge of the
eighth clock (SCL) pulse. If the addresses match, and
the BF and I2COV bits are clear, the following things
happen:
• I2CSR loaded into I2CBUF
• Buffer Full (BF) bit is set
• ACK pulse is generated
• I2C Interrupt Flag (I2CIF) is set (interrupt is
generated if enabled (I2CIE set) on falling edge of
ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 7-5). The five most
significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. The R/W bit (bit 0) must
specify a write, so the slave device will received the
second address byte. For a 10-bit address the first byte
would equal ‘1 1 1 1 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address are as follows, with steps 7-9 for
slave-transmitter:
1. Receive first (high) byte of address (I2CIF, BF
and UA are set).
2. Update I2CADD with second (low) byte of
address (clears UA and releases SCL line).
3. Read I2CBUF (clears BF) and clear I2CIF.
4. Receive second (low) byte of address (I2CIF, BF
and UA are set).
5. Update I2CADD with first (high) byte of address
(clears UA, if match releases SCL line).
6. Read I2CBUF (clears BF) and clear I2CIF
7. Receive Repeated START.
8. Receive first (high) byte of address (I2CIF and
BF are set).
9. Read I2CBUF (clears BF) and clear I2CIF.
7.5.1.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the I2CSTAT
register is cleared. The received address is loaded into
the I2CBUF.
When the address byte overflow condition exists then
no acknowledge (ACK) pulse is given. An overflow
condition is defined as either the BF bit (I2CSTAT<0>)
is set or the I2COV bit (I2CCON<6>) is set
(Figure 7-14).
An I2CIF interrupt is generated for each data transfer
byte. The I2CIF bit must be cleared in software, and the
I2CSTAT register is used to determine the status of the
byte. In master mode with slave enabled, three inter-
rupt sources are possible. Reading BF, P and S will
indicate the source of the interrupt.
Caution:
BF is set after receipt of eight bits and auto-
matically cleared after the I2CBUF is read.
However, the flag is not actually cleared
until receipt of the acknowledge pulse. Oth-
erwise extra reads appear to be valid.
FIGURE 7-14: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address R/W=0
SDA
A7 A6 A5 A4 A3 A2 A1
Receiving Data
ACK
Receiving Data
ACK
ACKD7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
I2CIF (PIR1<3>)
BF (I2CSTAT<0>)
I2COV (I2CCON<6>)
Cleared in software
I2CBUF is read
Bus Master
terminates
transfer
I2COV is set
because I2CBUF is
still full. ACK is not sent.
DS40122B-page 50
Preliminary
© 1996 Microchip Technology Inc.
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