PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
The internal and external registers implemented by the Switch Processor and the
associated ELAN 8x10 functional units, as well as the view of the debug registers from
the PCI bus interface, are presented in subsequent sections.
The Switch Processor expects to locate its operating firmware as part of a boot image
present in the external memory space. The format of the boot image is described later.
Ethernet MAC Interfaces
Eight identical interfaces to external Ethernet/IEEE 802.3 MAU devices are provided
on-chip. The ELAN 8x10 performs only the 802.3 MAC-layer functions: serial/ parallel
conversion, packet generation and extraction, jamming and backoff after collision,
deference, interframe gap enforcement, and buffering. These are performed with a
combination of dedicated hardware in the MAC interfaces and microcode running on
the Switch Processor. The external transceivers (MAU devices) are expected to
implement all the standard 10BaseT MAU functions: line driving/receiving, clock
generation and recovery, Manchester encoding and decoding, and carrier and collision
detect.
Each MAC interface unit consists of the following functional blocks:
• Interfaces to the receive and transmit ports of the external 10 Mb/s MAU
devices. These interfaces transfer serial, independently clocked receive and
transmit data between the ELAN 8x10 and the MAU, and also allow the MAU to
report carrier detect and collision status.
• A serializer/deserializer that converts between the 8-bit parallel data format used
by the ELAN 8x10 MAC logic and the 1-bit serial format used by the MAU.
• A 32-byte bi-directional FIFO buffer that holds parallel transmit data prior to
parallel-to-serial conversion, and receive data words after serial-to-parallel
conversion. The FIFO buffer also decouples the external MAU transmit and
receive clocks from the internal ELAN 8x10 device clock, and converts between
a byte-wide interface to the serializer/deserializer and a word-wide interface to
the DMA Controller.
• Control/status registers and logic that allows the Switch Processor to control the
MAC port and the MAU devices, and also to monitor status. The control/status
registers contain the timers required for the CSMA/CD algorithm.
During transmission, 32-bit parallel data to be transmitted are placed in the bi-
directional FIFO buffer of each MAC port by the DMA Controller. After any required
deference or interframe gap time, these are read out as 8-bit bytes, serialized and sent
to the external MAU for transmission on to the twisted-pair or coaxial link. The IEEE
802.3 standard 2-part interframe gap timing algorithm is implemented.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
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