PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
Note:
None of the MAC control, status or configuration registers are visible from the
PCI bus interface; they may be accessed only by the Switch Processor. More
details on individual registers within the MAC channels are given later.
Multichannel DMA Controller
The DMA Controller is responsible for performing all data block transfers within the
ELAN 8x10 and for computing the 32-bit Ethernet CRC check performed on packets
received from or transmitted to the MAU channels. A special feature of the DMA
Controller is its ability to automatically allocate buffer storage from a central free pool
(organized as a linked list pointed to by a dedicated device register) when receiving
data from a MAC channel or the expansion port. In addition, the DMA Controller
implements an address hash table look-up capability that automatically resolves the
source and destination MAC addresses of incoming Ethernet frames using an address
table built in external RAM.
The DMA Controller supports a total of eleven separate channels, all of which may be
running concurrently. Each channel is assigned a dedicated set of locations within an
internal register file to hold transfer parameters and status. All but two of the DMA
channels are capable of handling linked-lists of fixed-length packet buffers, which are
chained together in varying numbers to hold Ethernet packets of different lengths. The
eleven channels are dedicated to various functions as follows:
• Eight channels are used to perform data transfers between the 8 MAC channel
FIFOs and the local memory, copying data from the local memory to the MAC
FIFOs on transmit or from the FIFOs to the local memory on receive. These
channels are capable of generating (on receive) and following (on transmit)
linked-lists of packet buffers in external memory. A 32-bit CRC is computed on
both transmit and receive data transfers; the CRC result may be optionally
appended to the transmit data, and is accessible to the Switch Processor
firmware in the form of a CRC check error bit after a packet has been received.
Packet buffers are automatically allocated from a central free pool on receive.
The source and destination MAC addresses of frames received from the MAC
channels will also be extracted and used to look up the address entries in an
external hash table.
• One channel is used to perform block transfers from the external PCI expansion
bus to the local memory. This channel can follow a chain of remote source
packet buffers, reading data over the PCI bus and creating a corresponding
chain of packet buffers in the local memory, automatically allocating the required
local packet buffers from the free pool.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
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