PM4328 View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM4328' PDF : 250 Pages View PDF
STANDARD PRODUCT
DATASHEET
PMC-2011596
ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
T1 and E1 System Side Serial Clock and Data Interface
ICLK[1]/ISIG[1]
ICLK[2]/ISIG[2]
ICLK[3]/ISIG[3]
ICLK[4]/ISIG[4]
ICLK[5]/ISIG[5]
ICLK[6]/ISIG[6]
ICLK[7]/ISIG[7]
ICLK[8]/ISIG[8]
ICLK[9]/ISIG[9]
ICLK[10]/ISIG[10]
ICLK[11]/ISIG[11]
ICLK[12]/ISIG[12]
ICLK[13]/ISIG[13]
ICLK[14]/ISIG[14]
ICLK[15]/ISIG[15]
ICLK[16]/ISIG[16]
ICLK[17]/ISIG[17]
ICLK[18]/ISIG[18]
ICLK[19]/ISIG[19]
ICLK[20]/ISIG[20]
ICLK[21]/ISIG[21]
ICLK[22]/ISIG[22]
ICLK[23]/ISIG[23]
ICLK[24]/ISIG[24]
ICLK[25]/ISIG[25]
ICLK[26]/ISIG[26]
ICLK[27]/ISIG[27]
ICLK[28]/ISIG[28]
Output Y3 Ingress Clocks (ICLK[1:28]). The Ingress Clocks are
AB2 active when the external signaling interface is disabled.
AB20 Each ingress clock is optionally a smoothed (jitter
AB21 attenuated) version of the associated receive clock
W22 from the DS3 multiplexer. When the Clock Master:
Y20 NxChannel mode is active, ICLK[x] is a gapped version
H22 of the smoothed receive clock. When Clock Master:
F19 Full T1/E1 mode is active, IFP[x] and ID[x] are updated
W3 on the active edge of ICLK[x]. When the Clock Master:
AA1 NxDS0 mode is active, ID[x] is updated on the active
H3 edge of ICLK[x].
H1
L22
K19 Ingress Signaling (ISIG[1:28]). When the Clock
F22 Slave: External Signaling mode is enabled, each
G20 ISIG[x] contains the extracted signaling bits for each
T3 channel in the frame, repeated for the entire
U1 superframe. Each channel’s signaling bits are valid in
D1 bit locations 5,6,7,8 of the channel and are channel-
C1 aligned with the ID[x] data stream. ISIG[x] is updated
H19 on the active edge of the common ingress clock,
G19 CICLK.
E19
F21
K3 In E1 mode only ICLK[1:21] and ISIG[1:21] are used.
J4 ICLK[1]/ISIG[1] shares a pin with the DS3 system
E3 interface signal RGAPCLK/RSCLK.
D2
IFP[1]
IFP[2]
IFP[3]
IFP[4]
IFP[5]
IFP[6]
IFP[7]
IFP[8]
IFP[9]
IFP[10]
IFP[11]
Output AB5 Ingress Frame Pulse (IFP[1:28]). The IFP[x] outputs
V3 are intended as timing references.
W20
AA22
Y21
IFP[x] indicates the frame alignment or
alignment of the ingress stream, ID[x].
the
superframe
W21 When Clock Master: Full T1/E1 mode is active, IFP[x]
K22 is updated on the active edge of the associated
K21 ICLK[x]. When Clock Master: NxDS0 mode is active,
Y1 ICLK[x] is gapped during the pulse on IFP[x]. When
W1 the Clock Slave ingress modes are active, IFP[x] is
F4 updated on the active edge of CICLK. I the Clear
PROPRIETARY AND CONFIDENTIAL
32
Share Link: 
