PM4328 View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM4328' PDF : 250 Pages View PDF
STANDARD PRODUCT
DATASHEET
PMC-2011596
Pin Name
ID[25]
ID[26]
ID[27]
ID[28]
CICLK
CIFP
CTCLK
ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Type
Input
Input
Input
Pin Function
No.
J1
H4
B10
C10
N1 Common Ingress Clock (CICLK). CICLK is either a
1.544MHz clock in T1 mode or a 2.048MHz clock in T1
or E1 modes, with optional gapping for adaptation to
non-uniform backplane data streams. CICLK is
common to all 28 T1 or 21 E1 framers. CIFP is
sampled on the active edge of CICLK.
When the Clock Slave ingress modes are active, ID[x],
ISIG[x], and IFP[x] are updated on the active edge of
CICLK.
CICLK is a nominal 1.544 or 2.048 MHz clock +/-
50ppm with a 50% duty cycle.
This signal shares a pin with the H-MVIP signal
CMVFPC. By default this input is CICLK.
P4 Common Ingress Frame Pulse (CIFP). When the
elastic store is enabled (Clock Slave mode is active on
the ingress side), CIFP is used to frame align the
ingress data to the system frame alignment. CIFP is
common to all 28 T1 or 21 E1 framers. When frame
alignment is required, a pulse at least 1 CICLK cycle
wide must be provided on CIFP a maximum of once
every frame (nominally 193 or 256 bit times).
CIFP is sampled on the active edge of CICLK as
selected by the CIFE bit in the Master Common
Ingress Serial and H-MVIP Interface Configuration
register.
M3 Common Transmit Clock (CTCLK). This input signal
is used as a reference transmit tributary clock which
can be used in egress Clock Master modes.
Depending on the configuration of the TECT3, CTCLK
may be a line rate clock (so the transmit clock is
generated directly from CTCLK, or from CTCLK after
jitter attenuation), or a multiple of 8kHz (Nx8khz, where
1£N£256) so long as CTCLK is jitter-free when divided
down to 8kHz (in which case the transmit clock is
PROPRIETARY AND CONFIDENTIAL
34
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