PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
9 FUNCTIONAL DESCRIPTION
9.1 Serial to Parallel Converter
The Serial to Parallel Converter (SIPO) block provides the first stage of digital
processing of the receive incoming STS-1 or STS-3 bit serial data stream. The
byte alignment in the incoming stream is determined by searching for the 16 bit
frame alignment signal (A1, A2) for STS-1 mode, or the 48 bit frame alignment
signal (A1, A1, A1, A2, A2, A2) for STS-3 mode. The bit serial stream (RSIN, or
RXD+/-) is converted from serial to parallel format in accordance with the
determined byte alignment. The bit serial input clock (RSICLK, or RXC+/-) is
divided by eight to produce the GRICLK output. GRICLK must be connected
externally to RICLK when processing a bit serial stream.
Both TTL and PECL levels may be used at 51.84 Mbit/s, but only the PECL
inputs are available at 155.22 Mbit/s.
9.2 Receive Section Overhead Processor
The Receive Section Overhead Processor (RSOP) block processes the section
overhead (regenerator section) of the receive incoming stream. It can be
configured to process an STS-1, or STS-3/STM-1 data stream.
The RSOP block optionally descrambles the received data and extracts the data
communication channel, order wire channel and user channel from the section
overhead, and provides them as lower rate bit serial outputs (RSD, RSOW,
RSUC) together with associated clock signals (RSDCLK, and ROWCLK). The
complete descrambled SONET/SDH data stream is output by the STXC in byte
serial format. Line alarm indication signal is inserted in the byte serial output
data stream using input RLAIS or, optionally, automatically when loss-of-frame,
section trace or loss-of-signal events occur. The automatic insertion of AIS is
controlled by the AUTORAIS bit in the Ring Control Register.
Out-of-frame (OOF), loss-of-frame (LOF), and loss-of-signal (LOS) state outputs
are provided and section level bit-interleaved parity errors are accumulated. A
section BIP-8 error clock is also provided (B1E). A maskable interrupt is
activated by state transitions on the OOF, LOF, or LOS outputs, or by a single B1
error event. Microprocessor readable registers are provided that allow
accumulated B1 errors to be read out at intervals of up to one second duration.
The RSOP block frames to the data stream by operating with an upstream
pattern detector (the Serial to Parallel Converter block; or an external serial to
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 36
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