PQFP208 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PQFP208' PDF : 11 Pages View PDF
STi5500
CONFIDENTIAL III - INTERNAL CIRCUIT DESCRIPTION
A general block diagram for the STi5500 is shown
is Figure 1.
The performance offered by the ST20 32-bit micro-
core allows the following operations to be per-
formed in software :
1 Device drivers for Video, Audio and Sub-picture
Decoders
2 Audio/Video/Subpicture synchronisation
3 System management functions
4 Electronic program guide
5 Conditional access module
The use of a 32-bit CPU enables advanced graph-
ics routines to be employed for on-screen display
functions, allowing fast turnaround system up-
grades.
III.1 - The ST20 32-bit CPU
The ST20 micro-core family has been developed by
SGS-THOMSON Microelectronics to provide the
tools and building blocks to enable the development
of highly integrated application-specific 32-bit de-
vices at the lowest cost and fastest time to market.
The ST20 macrocell library includes the ST20Cx
family of 32-bit VL-RISC (variable length reduced
instruction set computer) micro-cores, embedded
memories, standard peripherals, I/O, controllers
and ASICs.
The STi5500 uses the ST20 macrocell library to
provide all of the dedicated hardware modules
required in a set top box or DVD system.
These include :
- High performance internal SRAM and cache sub-
system,
- I2C interfaces to other devices in the set top box,
- UART serial I/O interface to modem and auxiliary
ports,
- Interrupt controller for internal and external interrupts,
- DMA to MPEG audio and video device(s),
- External memory interface supporting DRAM,
EPROM and peripherals,
- PWM/timer modulefor control of systemclockVCXOs,
- Programmable I/O pins,
- Smart card interfaces.
III.2 - MPEG-2 Video/Audio Decoder
The video decoder implemented in the STi5500
uses a patented memory reduction/bandwidth re-
duction scheme to offer the user the best band-
width/memory size compromise.
The algorithm is lossless and uses "on-the-fly"
decoding to reduce the memory requirements to
2 frame buffers in memory size reduction mode.
When used in bandwidth reduction mode the mem-
6/11
ory usage is the normal three buffers but the band-
width required by the decoder is significantly re-
duced over a classical implementation.
In summary the features of this decoder core are :
- Video decoder fully supports MPEG-2 Main Pro-
file/Main Level (MP@ML),
- Memory reduction architecture allows sharing of
single 16MBit SDRAM between MPEG decoding,
micro and transport functions - memory expand-
able to 32Mbits of SDRAM,
- Letterbox filter,
- Horizontal and vertical image re-sizing,
- 2 to 8 bit OSD (6-bit luma resolution, 4-bit chroma
resolution),
- Accepts MPEG-2 Program Streams, PES and
MPEG-1 system streams,
- Automatic error concealment.
The output from the video decoder is fed directly to
a PAL/NTSC encoder unit generating simultane-
ously a composite video signal, component Y/C
and RGB for each of the two standards.
The signals can be optionally encoded following
the MacrovisionTM 7.01/6.1 specification if the user
has a licence to use the technology. The digital
encoder cell is also capable of encoding into the
composite signal teletext and closed caption infor-
mation.
The audio decoder performs MPEG levels 1 and
II decoding and is functionally equivalent to the
STi3520A audio decoder. The STi5500 has a dedi-
cated interface to an external Dolby AC3 decoder
whilst allowing audio buffering to be performed in
the 16 Mbit SDRAM.
III.3 - High Quality Graphics
The graphics performance of the STi5500 supports
the new requirements for intelligent program
guides and interactive applications.
The display interface supports up to 256 colours for
each OSD region and a transparency feature al-
lows mixing of video with the OSD. Fast access
graphics and many other additional features are
available and are supported by a graphics library.
Excellent system performance is obtained by
closely coupling the high performance RISC proc-
essor and cache with the MPEG audio/video core
and display memory.
Low latency RISC access and DMA engines allow
rapid construction of bit maps. DVD graphics are
also supported by an integrated sub picture de-
coder. Pan and scan and letterbox output are pro-
vided for 16:9 applications.
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