PQFP208 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PQFP208' PDF : 11 Pages View PDF
STi5500
CONFIDENTIAL III - INTERNAL CIRCUIT DESCRIPTION (continued)
III.4 - External Memory
The STi5500 has been designed to minimize sys-
tem costs. The external memory interface contains
and data memory. The processor can access mem-
ory via the general purpose External Memory Inter-
a zero glue logic DRAM controller and a low-cost face (EMI) or via the SDRAM EMI which is shared
16-bit EPROM interface.
with the MPEG decoder.
The STi5500 applies a unique memory architecture
which consolidates the system, on-screen display,
audio and video memory into a single memory chip.
Moreover, a patented memory management algo-
rithm allows the STi5500 to decode an MPEG2 MP
@ ML bitstream with CCIR601 NTSC pictures in
only 10.5 Mbits and with CCIR601 PAL pictures in
only 12MBits, with absolutely no impact on the
picture quality.
If 16MBits SDRAM is attached to the STi5500, then
4 Mbits or more are free for other purposes such
as full screen high resolution graphics and proces-
sor use. A second optional 16Mbit SDRAM can also
be added for applications which require more
graphics features such as full screen still image
display or processor memory.
III.5.3 - Memory Subsystem
The STi5500 on-chip SRAM memory system pro-
vides 160Mbytes/s internal data bandwidth, sup-
porting pipelined 2-cycle internal memory access
at 25 ns cycle times. The STi5500 memory system
consists of 2 Kbytes of SRAM, 2Kbytes of instruc-
tion cache, a 2Kbyte data cache that can be pro-
grammed to be SRAM, and an external memory
interface (EMI).
The STi5500 product has 2 Kbytes of on-chip
SRAM. The advantage of this is the ability to store
time critical code on chip, for instance interrupt
routines, software kernels or device drivers, and
even frequently used data without these being
flushed from the caches.
The STi5500 also has a generic processor inter-
face allowing DMA access to the SDRAM memory
by an external processor.
The SDRAM memory interface directly supports
100MHz SDRAMs providing the very high band-
widths to support MPEG decoding and display,
OSD drawing and display, and general system use.
Furthermore, the ST20 VL-RISC micro-core has
the highest code density of any 32-bit CPU, leading
to the lowest cost program ROM.
III.5 - STi5500 Functional Description
III.5.1 - STi5500 Functional Modules
Figure 1 shows the subsystem modules that com-
prise the STi5500. These modules are outlined
below and more detailed information is given in the
following chapters of this datasheet.
III.5.2 - CPU
The Central Processing Unit (CPU) on the STi5500
is the ST20-C2 32-bit processor core. It contains
instruction processing logic, instruction and data
pointers and an operand register. It directly ac-
cesses the high speed on-chip SRAM memory,
which can store data or programs, and uses the
Caches to reduce access time to off chip program
The instruction and data caches are direct mapped
with a write-back system for the data cache and
support burst accesses to the external memories
for refill and write-back which are effective for in-
creasing performance with page-mode and
SDRAM memories.
The STi5500 EMI controls access to the external
memory and peripherals while the SDRAM EMI
provides access to the SDRAM buffer for the
MPEG decoders, ST20 and DMA peripherals.
The STi5500 EMI can access a 16 Mbyte (or
greater if DRAM is used) physical address space
in each of the four general purpose memory banks,
and provides sustained transfer rates of up to
80Mbytes/s.
Peripherals that support an asynchronous data
acknowledge are supported as is an external
PowerPC which can share the bus with the
STi5500 and access the SDRAM buffer through
the device.
High memory bandwidths up to 200Mbytes/s can
be supported by the SDRAM EMI (see Figure 2).
The STi5500 internal memory interconnect provides
buffering and arbitration of memory access requests to
sustain very high throughput of memory accesses.
Figure 1 STi5500 architectural block diagram.
7/11
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