PQFP208 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PQFP208' PDF : 11 Pages View PDF
STi5500
CONFIDENTIAL III - INTERNAL CIRCUIT DESCRIPTION (continued)
Figure 2 : STi5500 Top-Level Architecture
LINK INTERFACE
CPU ARBITOR
SDRAM ARBITOR
SDRAM
AUDIO VIDEO
DENC
I - CACHE
SRAM D - CACHE
COMPRESSED DATA/REGISTER BUS
CPU
CENTRAL COMMAND PORT
ST-20
ARBITOR
ST-20 EMI
ROM
DRAM
SRAM
PWM
MPEG DMA
I2C
UART
BLOCK MOVE DMA
MPEG DMA
COMMUNICATIONS
ARBITOR
PERIPHERAL DMA
III.5.4 - System services module
The STi5500 system services module includes :
- phase locked loop (PLL) - accepts 27MHz input
and generates all the internal high frequency
clocks needed for the CPU and the OS-Link.
- Test access port - JTAG compatible,
- Diagnostics controller accessed via the JTAG
port providing :
- Bootstrapping during development,
- Hardware breakpoint and watchpoint,
- Real time trace,
- External LSA triggering support.
III.5.5 - Serial Communications
To facilitate the connection of this system the front
end device and other peripherals, two UARTs
(ASCs) are included in the device. The UARTs
provide an asynchronous serial interface. The
UART can be programmed to support a range of
baud rates and data formats, for example, data
size, stop bits and parity. Two synchronous serial
communications (SSC) interfaces are provided on
the device. These can be used for a remote control
device for example via an I2C or SPI bus.
III.5.6 - Interrupt Subsystem
The STi5500 interrupt subsystem supports eight
prioritized interrupt levels. Four external interrupt
pins are provided. Level assignment logic allows
any of the internal or external interrupts to be as-
signed and, if necessary, share any interrupt level.
8/11
III.5.7 - Link Interface
The link interface is an integrated transport stream
processor which accepts either DSS or DVB
streams on a serial interface with a front-end de-
vice. The interface performs the demultiplexing
operations with no interaction from the ST20. In
summary the features of the interface are :
- Framing of transport packets (SYNC byte detection),
- PID filtering of up to 32 PIDs,
- Descrambling to DVB/DES standard - transport
or PES level (DVB),
- Adaptation field parsing - detection and time
stamping. System time clock adjustment handled
by software.
- Section filtering - 32 filters,
- Demultiplexing of transport stream by PID,
- DMA and buffering of streams in memory with
communication to CPU of buffer state,
- DMA of two of the streams to the audio and video
MPEG decoder compressed data FIFOs.
In addition to these transport device functions the
interface can copy the entire transport stream or
selected PIDs from the transport stream through an
SDAV (high speed bi-directional serial bus) interface.
Communication with the ST20 is made via inter-
rupts and a shared memory space. The ST20 can
place filter values, DMA destinations and descram-
bling keys, for example, in the shared memory to
be picked up later during demultiplexing/descram-
bling operations.
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