QL5130-33APF144I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5130-33APF144I
QuickLogic Corporation
'QL5130-33APF144I' PDF : 17 Pages View PDF
QL5130 - QuickPCITM
Internal Interface
InternSailgInntaerlfaDceeSsicgnraipl Dteioscnrisptions
Signals used to connect to the PCI interface in the QL5130 are described below. The direction of the signal indi-
cates if it is an input provided by the local interface (I) or an output provided by the PCI interface (O).
Usr_Addr_WrData[31:0]
Usr_CBE[3:0]
Usr_Adr_Valid
Usr_Adr_Inc
Usr_RdDecode
Usr_WrDecode
O Target address, and data from target writes. During all target
accesses, the address will be presented on
Usr_Addr_WrData[31:0] and simultaneously, Usr_Adr_Valid will
be active. During target write transactions, this port will also
present write data to the PCI configuration space or user logic.
O PCI command and byte enables. During target accesses, the PCI
command will be presented on Usr_CBE[3:0] and simultaneously,
Usr_Adr_Valid will be active. During target read or write
transactions, this port will present active-low byte-enables to the
PCI configuration space or user logic.
O Indicates the beginning of a PCI transaction, and that a target
address is valid on Usr_Addr_WrData[31:0] and the PCI
command is valid on Usr_CBE[3:0]. When this signal is active,
the target address must be latched and decoded to determine if this
address belongs to the device’s memory space. Also, the PCI
command must be decoded to determine the type of PCI
transaction. On subsequent clocks of a target access, this signal
will be low, indicating that an address is NOT present on
Usr_Addr_WrData[31:0].
O Indicates that the target address should be incremented, because
the previous data transfer has completed. During burst target
accesses, the target address is only presented to the back-end logic
at the beginning of the transaction (when Usr_Adr_Valid is
active), and must therefore be latched and incremented (by 4) for
subsequent data transfers. Note that during write transactions,
Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that
must be accepted by the back-end logic (regardless of the state of
Usr_Rdy). During read transactions, Usr_Adr_Inc will signal to
the back-end that the PCI core is ready to accept data.
Usr_Adr_Inc and Usr_Rdy both active during a read transaction
signals a data transfer between the FPGA and the PCI core (and
that the address counter must be incremented).
I This signal should be driven active when a “user read” command
has been decoded from the Usr_CBE[3:0] bus (while
Usr_Adr_Valid is active). This command may be mapped from
any of the PCI “read” commands, such as Memory Read, Memory
Read Line, Memory Read Multiple, I/O Read, etc.
I This signal should be driven active when a “user write” command
has been decoded from the Usr_CBE[3:0] bus (while
Usr_Adr_Valid is active). This command may be mapped from
any of the PCI “write” commands, such as Memory Write or I/O
Write.
4
Rev B
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