QL5130-33APF144I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5130-33APF144I
QuickLogic Corporation
'QL5130-33APF144I' PDF : 17 Pages View PDF
QL5130 - QuickPCITM
Internal Interface Signal Descriptions (Continued)
Usr_Select
Usr_Write
Cfg_Write
Cfg_RdData[31:0]
Usr_RdData[31:0]
Cfg_CmdReg8
Cfg_CmdReg6
Cfg_PERR_Det
Cfg_SERR_Sig
Usr_TRDYN
Usr_STOPN
Usr_Devsel
Usr_Last_Cycle_D1
RdPipe_Stat[1:0]
Usr_Rdy
Usr_Stop
I This signal should be driven active when the address on
Usr_Addr_WrData[31:0] has been decoded and determined to be
within the address space of the device. Usr_Addr_WrData[31:0]
must be compared to each of the valid Base Address Registers in
the PCI configuration space. Also, this signal must be gated by the
Memory Access Enable or I/O Access Enable registers in the PCI
configuration space (Command Register bits 1 or 0 at offset 04h).
O This signal will be active throughout a “user write” transaction,
which has been decoded by Usr_WrDecode at the beginning of the
transaction. The write-enable for individual double-words of data
(on Usr_Addr_WrData[31:0]) during a user write transaction
should be generated by logically ANDing this signal with
Usr_Adr_Inc.
O This signal will be active throughout a configuration write
transaction. The write-enable for individual double-words of data
(on Usr_Addr_WrData[31:0]) during a configuration write
transaction should be generated by logically ANDing this signal
with Usr_Adr_Inc.
I Data from the PCI configuration registers, required to be presented
to the PCI core during PCI configuration reads.
I Data from the back-end user logic, required to be presented during
PCI reads.
I Bits 6 and 8 from the Command Register in the PCI configuration
space (offset 04h).
O Parity error detected on the PCI bus. When this signal is active, bit
15 of the Status Register must be set in the PCI configuration
space (offset 04h).
O System error asserted on the PCI bus. When this signal is active,
the Signaled System Error bit, bit 14 of the Status Register, must
be set in the PCI configuration space (offset 04h).
O Copy of the TRDYN signal as driven by the PCI target interface.
O Copy of the STOPN signal as driven by the PCI target interface.
O Inverted copy of the DEVSELN signal as driven by the PCI target
interface.
O Indicates that the last transfer in a PCI transaction is occurring.
O Indicates the number of dwords currently in the read pipeline
(“00” = 0 elements, “01” = 1 element, “11” = 2 elements). This
value is important at the end of a transaction (i.e. when
Usr_Last_Cycle_D1 is active) if non-prefetchable memory is
being read. Non-prefetchable memory is defined as registers or
memory elements whose value changes when they are read.
Examples are status registers which are cleared when they are
read, or FIFO memories, since consecutive reads from the same
address in these elements may not produce the same data values.
I Used to delay (add wait states to) a PCI transaction when the back
end needs additional time. Subject to PCI latency restrictions.
I Used to prematurely stop a PCI target access on the next PCI
clock.
Rev B
5
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