QL5130-33APF144I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5130-33APF144I
QuickLogic Corporation
'QL5130-33APF144I' PDF : 17 Pages View PDF
QL5130 - QuickPCITM
ARRAY OF LOGIC CELLS
Array of Logic Cells
A wide range of additional features complements the
QL5130 device. The FPGA portion of the device is
5 volt and 3.3-volt PCI-compliant and can perform
high-speed logic functions such as 160 MHz FIFOs.
I/O pins provide individually controlled output
enables, dedicated input/feedback registers, and full
JTAG capability for boundary scan and test. In addi-
tion, the QL5130 device provides the benefits of
non-volatility, high design security, immediate func-
tionality on power-up, and a single chip solution.
The QL5130 programmable logic architecture con-
sists of an array of user-configurable logic building
blocks, called logic cells, set beneath a grid of metal
wiring channels similar to those of a gate array.
Through ViaLink® elements located at the wire inter-
sections, the output(s) of any cell may be pro-
grammed to connect to the input(s) of any other cell.
Using the programmable logic in the QL5130,
designers can quickly and easily customize their
“back-end” design for any number of applications.
RAM MODULE FEATURES
RAM Module Features
The QL5130 device has twelve 1,152-bit RAM mod-
ules, for a total of 13,824 RAM bits. Using two
“mode” pins, designers can configure each module
into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2
blocks. See the figure below. The blocks are also
easily cascadable to increase their effective width or
depth.
RAM Module
MODE[1:0]
W A[a:0]
W D[w:0]
ASYNCRD
RA[a:0]
RD[w:0]
WE
W CLK
RE
RCLK
QS
A1
A2
A3
A4
AZ
A5
A6
OS
OP
B1
B2
C1
OZ
C2
MP
MS
QZ
D1
D2
E1
E2
NP
NZ
NS
F1
F2
F3
F4
FZ
F5
F6
QC
QR
FIGURE 4. Logic Cell
FIGURE 5. RAM Module
Mode:
64x18
128x9
256x4
512x2
Address
Buses [a:0]
[5:0]
[6:0]
[7:0]
[8:0]
Data Buses
[w:0]
[17:0]
[8:0]
[3:0]
[1:0]
6
Rev B
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