QL5130-33APF144I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5130-33APF144I
QuickLogic Corporation
'QL5130-33APF144I' PDF : 17 Pages View PDF
QL5130 - QuickPCITM
EXTERNAL DEVICE PINS
External Device Pins
Pin/Bus Name
AD[31:0]
CBEN[3:0]
PAR
FRAMEN
DEVSELN
CLK
RSTN
PERRN
SERRN
IDSEL
IRDYN
TRDYN
STOPN
Type
T/S
T/S
T/S
S/T/S
S/T/S
IN
IN
S/T/S
O/D
IN
S/T/S
S/T/S
S/T/S
Function
PCI Address and Data: 32 bit multiplexed address/data
bus.
PCI Bus Command and Byte Enables: Multiplexed bus
which contains byte enables for AD[31:0] or the Bus
Command during the address phase of a PCI transac-
tion.
PCI Parity: Even Parity across AD[31:0] and C/
BEN[3:0] busses. Driven one clock after address or
data phases. Master drives PAR on address cycles and
PCI writes. The Target drives PAR on PCI reads.
PCI Cycle Frame: Driven active by current PCI Master
during a PCI transaction. Driven low to indicate the
address cycle, driven high at the end of the transaction.
PCI Device Select. Driven by a Target that has decoded
a valid base address.
PCI System Clock Input.
PCI System Reset Input
PCI Data Parity Error. Driven active by the initiator or
target two clock cycles after a data parity error is
detected on the AD and C/BEN busses.
PCI System Error: Driven active when an address cycle
parity error, data parity error during a special cycle, or
other catastrophic error is detected.
PCI Initialization Device Select. Use to select a specific
PCI Agent during System Initialization.
PCI Initiator Ready. Indicates the Initiator’s ability to
complete a read or write transaction. Data transfer
occurs only on clock cycles where both IRDYN and
TRDYN are active.
PCI Target Ready. Indicates the Target’s ability to com-
plete a read or write transaction. Data transfer occurs
only on clock cycles where both IRDYN and TRDYN
are active.
PCI Stop. Used by a PCI Target to end a burst transac-
tion.
Rev B
9
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