QL5232-33APB456I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5232-33APB456I

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM

QuickLogic Corporation 

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QL5232 - QuickPCITM

QL5032 External Device Pins

QL5232 External Device Pins

Pin/Bus Name

AD[31:0]

CBEN[3:0]

PAR

FRAMEN

DEVSELN

CLK

RSTN

REQN

GNTN

PERRN

SERRN

IDSEL

IRDYN

TRDYN

STOPN

INTAN

Type

T/S

T/S

T/S

S/T/S

S/T/S

IN

IN

T/S

IN

S/T/S

O/D

IN

S/T/S

S/T/S

S/T/S

O/D

Function

PCI Address and Data: 32 bit multiplexed address/data bus.

PCI Bus Command and Byte Enables: Multiplexed bus which

contains byte enables for AD[31:0] or the Bus Command

during the address phase of a PCI transaction.

PCI Parity: Even Parity across AD[31:0] and C/BEN[3:0]

busses. Driven one clock after address or data phases. Mas-

ter drives PAR on address cycles and PCI writes. The Target

drives PAR on PCI reads.

PCI Cycle Frame: Driven active by current PCI Master dur-

ing a PCI transaction. Driven low to indicate the address

cycle, driven high at the end of the transaction.

PCI Device Select. Driven by a Target that has decoded a

valid base address.

PCI System Clock Input.

PCI System Reset Input

PCI Request. Indicates to the Arbiter that this PCI Agent (Ini-

tiator) wishes to use the bus. A point to point signal between

the PCI Device and the System Arbiter.

PCI Grant. Indicates to a PCI Agent (Initiator) that it has

been granted access to the PCI bus by the Arbiter. A point to

point signal between the PCI device and the System

Arbiter.

PCI Data Parity Error. Driven active by the initiator or target

two clock cycles after a data parity error is detected on the

AD and C/BE# busses.

PCI System Error: Driven active when an address cycle par-

ity error, data parity error during a special cycle, or other

catastrophic error is detected.

PCI Initialization Device Select. Use to select a specific PCI

Agent during System Initialization.

PCI Initiator Ready. Indicates the Initiator’s ability to com-

plete a read or write transaction. Data transfer occurs only

on clock cycles where both IRDYN and TRDYN are active.

PCI Target Ready. Indicates the Target’s ability to complete

a read or write transaction. Data transfer occurs only on

clock cycles where both IRDYN and TRDYN are active.

PCI Stop. Used by a PCI Target to end a burst transaction.

Interrupt A. Asynchronous Active-Low Interrupt Request.

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PreliRmev iBnary

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