QL5232-33APB456I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5232-33APB456I
QuickLogic Corporation
'QL5232-33APB456I' PDF : 18 Pages View PDF
QL5232 - QuickPCITM
PCI Internal Signals
PCI Internal Signals
PCI_clock
PCI_reset
PCI_IRDYN_D1
PCI_FRAMEN_D1
PCI_DEVSELN_D1
PCI_TRDYN_D1
PCI_STOPN_D1
PCI_IDSEL_D1
O PCI clock.
O PCI reset signal.
O Copy of the IRDYN signal from the PCI bus, delayed by one clock.
O Copy of the FRAMEN signal from the PCI bus, delayed by one clock.
O Copy of the DEVSELN signal from the PCI bus, delayed by one clock.
O Copy of the TRDYN signal from the PCI bus, delayed by one clock.
O Copy of the STOPN signal from the PCI bus, delayed by one clock.
O Copy of the IDSEL signal from the PCI bus, delayed by one clock.
RARMAMMMoodduulleeFFeaetautruesres
The QL5232 device has twenty-two 1,152-bit RAM
modules, for a total of 25,344 RAM bits. Using two
“mode” pins, designers can configure each module
into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2
blocks. See the figure below. The blocks are also
easily cascadable to increase their effective width or
depth.
The RAM modules are “dual-ported”, with
completely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports
support asynchronous and synchronous operation,
while the WRITE ports support synchronous
operation. Each port has 18 data lines and 9 address
lines, allowing word lengths of up to 18 bits and
address spaces of up to 512 words. Depending on
the mode selected, however, some higher order data
or address lines may not be used.
The Write Enable (WE) line acts as a clock enable for
synchronous write operation. The Read Enable (RE)
acts as a clock enable for synchronous READ
operation (ASYNCRD input low), or as a flow-
through enable for asynchronous READ operation
(ASYNCRD input high).
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules. This
approach allows up to 512-deep configurations as
large as 28 bits wide in the QL5232 device.
A similar technique can be used to create depths
greater than 512 words. In this case address signals
higher than the eighth bit are encoded onto the write
enable (WE) input for WRITE operations. The READ
data outputs are multiplexed together using encoded
higher READ address bits for the multiplexer
SELECT signals.
RAM Module
MODE[1:0] ASYNCRD
WA[a:0]
RA[a:0]
WD[w:0]
RD[w:0]
WE
WCLK
RE
RCLK
FIGURE 4. RAM Module
64x18
128x9
256x4
512x2
Address
Buses [a:0]
[5:0]
[6:0]
[7:0]
[8:0]
Data Buses
[w:0]
[17:0]
[8:0]
> @
[1:0]
7
Rev B
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