QL5232-33APB456I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5232-33APB456I
QuickLogic Corporation
'QL5232-33APB456I' PDF : 18 Pages View PDF
QL5232 - QuickPCITM
PCI Master Interface
PCI Master Interface
The internal signals used to interface with the PCI controller in the QL5232 are listed below, along with a
description of each signal. The direction of the signal indicates if it is an input provided by the local interface (i) or
an output provided by the PCI controller (o). Signals that end with the character ‘N’ should be considered active-
low (for example, Mst_IRDYN
Mst_WrAd[31:0]
Mst_RdAd[31:0]
Mst_WrMode
Mst_RdMode
Mst_Burst_Req
Mst_One_Read
Mst_Two_Reads
Mst_WrData[31:0]
Mst_WrData_Valid
Mst_WrData_Rdy
Mst_WrBurst_Done
Mst_RdData[31:0]
Mst_RdData_Valid
Mst_RdBurst_Done
Mst_RdCmd[1:0]
Mst_LatCntEn
Mst_Xfer_D1
Mst_Last_Cycle
Mst_REQN
Mst_IRDYN
Mst_Tabort_Det
Mst_TTO_Det
I Address for master DMA writes. This address must be treated as valid from the
beginning of a DMA burst write until the DMA write operation is complete. It must
be incremented (by 4) each time data is transferred on the PCI bus, since only
DWORD (4 byte) transfers are supported.
I Address for master DMA reads. This address must be treated as valid from the
beginning of a DMA burst read until the DMA read operation is complete. It must be
incremented (by 4) each time data is transferred on the PCI bus, since only DWORD
(4 byte) transfers are supported.
I DMA state machine in “write” mode. This must be asserted at the beginning of a
Master Transfer, and must be held until the Master Transfer completed
(Mst_WrBurst_Done).
I DMA state machine in “read” mode. This must be asserted at the beginning of a
Master Transfer, and must be held until the Master Transfer completed
(Mst_RdBurst_Done).
I Request use of the PCI bus. This signal should be held from when the DMA
controller is ready to provide the first data, until the transfer is complete
(Mst_WrBurst Done or Mst_RdBurst_Done).
I This signals to the PCI core that one data transfer remains in the burst. This signal
must be asserted when only one DWORD remains to be transferred on the PCI bus.
I Two or less data transfers remain in the burst. This signal must be asserted when two
or less DWORDs remain to be transferred on the PCI bus.
I Data for master DMA writes (to PCI bus).
I Data valid on Mst_WrData[31:0].
O Data receive acknowledge for Mst_WrData[31:0]. This serves as a POP control for a
FIFO which provides data to the PCI core.
O Master write pipeline is empty, which indicates that the Write burst transaction is
completed.
O Data for master DMA reads (from PCI bus).
O Data valid on Mst_RdData[31:0]. This serves as a PUSH control for a FIFO that
receives data from the PCI core.
O Master read pipeline is empty, which indicates that Read burst transaction is
completed.
I Type of PCI read command to be used for DMA reads:
00 or 01 = Memory Read
10 = Memory Read Line
11 = Memory Read Multiple
I Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration
space (offset 0Ch). For full PCI compliance, this port should be always set to 1.
O Data was transferred on the previous PCI clock. Useful for updating DMA transfer
counts on DMA Read operations.
O Active during the last data transfer of a PCI master transaction.
O The PCI REQN signal generated by this device as PCI master. Not usually used in the
back-end design.
O The PCI IRDYN signal generated by this device as PCI master. Not usually used in
the back-end design.
O Target abort detected during master transaction. This is normally an error condition to
be handled in the DMA controller.
O Target timeout detected (no response from target). This is normally an error condition
to be handled in the DMA controller.
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PreliRmev iBnary
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